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2-3 features ? mitel st-bus compatible ? 8-line x 32-channel inputs ? 8-line x 32-channel outputs ? 256 ports non-blocking switch ? single power supply (+5 v) ? low power consumption: 30 mw typ. ? microprocessor-control interface ? three-state serial outputs description this vlsi iso-cmos device is designed for switching pcm-encoded voice or data, under microprocessor control, in a modern digital exchange, pbx or central of?ce. it provides simultaneous connections for up to 256 64 kbit/s channels. each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s st-bus stream. in addition, the mt8980 provides microprocessor read and write access to individual st-bus channels. figure 1 - functional block diagram sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 serial to parallel converter data memory frame counter control register control interface output mux connection memory parallel to serial converter cs r/ w a5/ a0 dta d7/ d0 csto c4i f0i v dd v ss ode sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 ds issue8 march 1997 mt8980d digital switch iso-cmos st-bus ? family ordering information mt8980de 40 pin plastic dip mt8980dp 44 pin plcc -40 c to +85 c
mt8980d 2-4 figure 2 - pin connections pin description pin # name description 40 dip 44 plcc 12 dt a data acknowledgement (open drain output). this is the data acknowledgement on the microprocessor interface. this pin is pulled low to signal that the chip has processed the data. a 909 w , 1/4w, resistor is recommended to be used as a pullup. 2-4 3-5 sti0- sti2 st-bus input 0 to 2 (inputs). these are the inputs for the 2048 kbit/s st-bus input streams. 5-9 7-11 sti3- sti7 st-bus input 3 to 7 (inputs). these are the inputs for the 2048 kbit/s st-bus input streams. 10 12 v dd power input. positive supply. 11 13 f0i framing 0-type (input). this is the input for the frame synchronization pulse for the 2048 kbit/s st-bus streams. a low on this input causes the internal counter to reset on the next negative transition of c4i. 12 14 c4i 4.096 mhz clock (input). st-bus bit cell boundaries lie on the alternate falling edges of this clock. 13- 15 15- 17 a0-a2 address 0 to 2 (inputs). these are the inputs for the address lines on the microprocessor interface. 16- 18 19- 21 a3-a5 address 3 to 5 (inputs). these are the inputs for the address lines on the microprocessor interface. 19 22 ds data strobe (input). this is the input for the active high data strobe on the microprocessor interface. 20 23 r/ w read or write (input). this is the input for the read/write signal on the microprocessor interface - high for read, low for write. 21 24 cs chip select (input). this is the input for the active low chip select on the microprocessor interface 1 6 5 4 3 2 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 23 18 19 20 21 22 24 25 26 27 28 17 29 sti3 sti4 sti5 sti6 sti7 vdd f0i c4i a0 a1 a2 sto3 sto4 sto5 sto6 sto7 vss d0 d1 d2 d3 d4 nc sti1 dta ode sto1 nc nc a4 ds cs d6 nc a3 a5 r/ w d7 d5 44 pin plcc dta sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 vdd f0i c4i a0 a1 a2 a3 a4 a5 ds csto ode sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 vss d0 d1 d2 d3 d4 d5 d6 d7 cs 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 r/ w 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 pin plastic dip sti2 sti0 csto sto0 sto2
mt8980d 2-5 22- 24 25- 27 d7-d5 data 7 to 5 (three-state i/o pins). these are the bidirectional data pins on the microprocessor interface. 25- 29 29- 33 d4-d0 data 4 to 0 (three-state i/o pins). these are the bidirectional data pins on the microprocessor interface. 30 34 v ss power input. negative supply (ground). 31- 35 35- 39 sto7- sto3 st-bus output 7 to 3 (three-state outputs). these are the pins for the eight 2048 kbit/s st-bus output streams. 36- 38 41- 43 sto2- sto0 st-bus output 2 to 0 (three-state outputs). these are the pins for the eight 2048 kbit/s st-bus output streams. 39 44 ode output drive enable (input). if this input is held high, the sto0-sto7 output drivers function normally. if this input is low, the sto0-sto7 output drivers go into their high impedance state. nb: even when ode is high, channels on the sto0-sto7 outputs can go high impedance under software control. 40 1 csto control st-bus output (complementary output). each frame of 256 bits on this st-bus output contains the values of bit 1 in the 256 locations of the connection memory high. 6, 18, 28, 40 nc no connection. pin description (continued) pin # name description 40 dip 44 plcc
mt8980d 2-6 functional description in recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems. in accordance with these trends, mitel has devised the st-bus (serial telecom bus). this bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. the uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future. the serial streams of the st-bus operate continuously at 2048 kbit/s and are arranged in 125 m s wide frames which contain 32 8-bit channels. mitel manufactures a number of devices which interface to the st-bus; a key device being the mt8980 chip. the mt8980 can switch data from channels on st- bus inputs to channels on st-bus outputs, and simultaneously allows its controlling microprocessor to read channels on st-bus inputs or write to channels on st-bus outputs (message mode). to the microprocessor, the mt8980 looks like a memory peripheral. the microprocessor can write to the mt8980 to establish switched connections between input st-bus channels and output st-bus channels, or to transmit messages on output st-bus channels. by reading from the mt8980, the microprocessor can receive messages from st-bus input channels or check which switched connections have already been established. by integrating both switching and interprocessor communications, the mt8980 allows systems to use distributed processing and to switch voice or data in an st-bus architecture. hardware description serial data at 2048 kbit/s is received at the eight st- bus inputs (sti0 to sti7), and serial data is transmitted at the eight st-bus outputs (sto0 to sto7). each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a pcm-encoded analog/voice sample as provided by a codec (e.g., mitels mt8964). this serial input word is converted into parallel data and stored in the 256 x 8 data memory. locations in the data memory are associated with particular channels on particular st-bus input streams. these locations can be read by the microprocessor which controls the chip. locations in the connection memory, which is split into high and low parts, are associated with particular st-bus output streams. when a channel is due to be transmitted on an st-bus output, the data for the channel can either be switched from an st-bus input or it can originate from the microprocessor. if the data is switched from an input, then the contents of the connection memory low location associated with the output channel is used to address the data memory. this data memory address corresponds to the channel on the input st-bus stream on which the data for switching arrived. if the data for the output channel originates from the microprocessor (message mode), then the contents of the connection memory low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. the connection memory data is received, via the control interface, at d7 to d0. the control interface also receives address information at a5 to a0 and handles the microprocessor control signals cs, dt a, r/ w and ds. there are two parts to any address in the data memory or connection memory. figure 3- address memory map a5 a4 a3 a2 a1 a0 hex address location 0 1 1 ? ? ? 1 x 0 0 ? ? ? 1 x 0 0 ? ? ? 1 x 0 0 ? ? ? 1 x 0 0 ? ? ? 1 x 0 1 ? ? ? 1 00 - 1f 20 21 ? ? ? 3f control register * channel 0 ? channel 1 ? ? ? ? channel 31 ? * writing to the control register is the only fast transaction. ? memory and stream are speci?ed by the contents of the control register.
mt8980d 2-7 the higher order bits come from the control register, which may be written to or read from via the control interface. the lower order bits come from the address lines directly. the control register also allows the chip to broadcast messages on all st-bus outputs (i.e., to put every channel into message mode), or to split the memory so that reads are from the data memory and writes are to the connection memory low. the connection memory high determines whether individual output channels are in message mode, and allows individual output channels to go into a high-impedance state, which enables arrays of mt8980s to be constructed. it also controls the csto pin. all st-bus timing is derived from the two signals c4i and f0i. software control the address lines on the control interface give access to the control register directly or, depending on the contents of the control register, to the high or low sections of the connection memory or to the data memory. if address line a5 is low, then the control register is addressed regardless of the other address lines (see fig. 3). if a5 is high, then the address lines a4-a0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the control register. the data in the control register consists of mode control bits, memory select bits, and stream address bits (see fig. 4). the memory select bits allow the connection memory high or low or the data memory to be chosen, and the stream address bits de?ne one of the st-bus input or output streams. bit 7 of the control register allows split memory operation - reads are from the data memory and writes are to the connection memory low. the other mode control bit, bit 6, puts every output channel on every output stream into active message mode; i.e., the contents of the connection memory low are output on the st-bus output streams once every frame unless the ode pin is low. in this mode the chip behaves as if bits 2 and 0 of every connection memory high location were 1, regardless of the actual values. figure 4 - control register bits bit name description 7 split memory when 1, all subsequent reads are from the data memory and writes are to the connection memory low, except when the control register is accessed again. when 0, the memory select bits specify the memory for subsequent operations. in either case, the stream address bits select the subsection of the memory which is made available. 6 message mode when 1, the contents of the connection memory low are output on the serial output streams except when the ode pin is low. when 0, the connection memory bits for each channel determine what is output. 5 (unused) 4-3 memory select bits 0-0 - not to be used 0-1 - data memory (read only from the microprocessor port) 1-0 - connection memory low 1-1 - connection memory high 2-0 stream address bits the number expressed in binary notation on these bits refers to the input or output st-bus stream which corresponds to the subsection of memory made accessible for subsequent operations. 76 5432 10 mode control bits (unused) memory select bits stream address bits
mt8980d 2-8 figure 5 - connection memory high bits figure 6 - connection memory low bits bit name description 2 message channel when 1, the contents of the corresponding location in connection memory low are output on the locations channel and stream. when 0, the contents of the corresponding location in connection memory low act as an address for the data memory and so determine the source of the connection to the locations channel and stream. 1 csto bit this bit is output on the csto pin one channel early. the csto bit for stream 0 is output ?rst. 0 output enable if the ode pin is high and bit 6 of the control register is 0, then this bit enables the output driver for the locations channel and stream. this allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. a 1 enables the driver and a 0 disables it. bit name description 7-5* stream address bits* the number expressed in binary notation on these 3 bits is the number of the st-bus stream for the source of the connection. bit 7 is the most signi?cant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on sti4. 4-0* channel address bits* the number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (the st-bus stream where the channel lies is de?ned by bits 7, 6 and 5.). bit 4 is the most signi?cant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19. *if bit 2 of the corresponding connection high location is 1 or if bit 6 of the control register is 1, then these entire 8 bits are output on the channel and stream associated with this location. otherwise, the bits are used as indicated to de?ne the source of the connection which is output on the channel and stream associated with this location. 76 5432 10 no corresponding memory - these bits give 0s if read. per channel control bits 76 5432 10 stream address bits channel address bits
mt8980d 2-9 if bit 6 of the control register is 0, then bits 2 and 0 of each connection memory high location function normally (see fig. 5). if bit 2 is 1, the associated st- bus output channel is in message mode; i.e., the byte in the corresponding connection memory low location is transmitted on the stream at that channel. otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the connection memory low de?ne the st-bus input stream and channel where the byte is to be found (see fig. 6). if the ode pin is low, then all serial outputs are high- impedance. if it is high and bit 6 in the control register is 1, then all outputs are active. if the ode pin is high and bit 6 in the control register is 0, then the bit 0 in the connection memory high location enables the output drivers for the corresponding individual st-bus output stream and channel. bit 0=1 enables the driver and bit 0=0 disables it (see fig. 5). bit 1 of each connection memory high location (see fig. 5) is output on the csto pin once every frame. to allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the st-bus streams, and the bit for stream 0 is output ?rst in the channel; e.g., bit 1s for channel 9 of streams 0-7 are output synchronously with st-bus channel 8 bits 7-0. applications use in a simple digital switching system figs. 7 and 8 show how mt8980s can be used with mt8964s to form a simple digital switching system. fig. 7 shows the interface between the mt8980s and the ?lter/codecs. fig. 8 shows the position of these components in an example architecture. the mt8964 ?lter/codec in fig. 7 receives and transmits digitized voice signals on the st-bus input d r , and st-bus output d x , respectively. these signals are routed to the st-bus inputs and outputs on the top mt8980, which is used as a digital speech switch. the mt8964 is controlled by the st-bus input d c originating from the bottom mt8980, which generates the appropriate signals from an output channel in message mode. this architecture optimizes the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an st-bus output. this signalling st-bus output is monitored by a microprocessor (not shown) through an st-bus input on the bottom mt8980. fig. 8 shows how a simple digital switching system may be designed using the st-bus architecture. this is a private telephone network with 256 extensions which uses a single mt8980 as a speech switch and a second mt8980 for communication with the line interface circuits. a larger digital switching system may be designed by cascading a number of mt8980s. fig. 9 shows how four mt8980s may be arranged in a non-blocking con?guration which can switch any channel on any of the st-bus inputs to any channel on the st-bus outputs. figure 7 - example of typical interface between 8980s and 8964s for simple digital switching system 8980 used as speech switch mt8980 sto0 sti0 sto0 sti0 mt8980 8980 used in message mode for control and signalling d x d r d c mt8964 filter/codec signalling logic line driver and 2- to 4- wire converter line interface circuit with 8964 filter/codec
mt8980d 2-10 figure 8 - example architecture of a simple digital switching system controlling micro- processor speech switch - 8980 control & signalling - 8980 sto0-7 sti0-7 sto0-7 line interface circuit with codec (e.g. 8964) line 1 line 256 line interface circuit with codec (e.g.8964) 8 8 8 8 ? ? ? repeated for lines 2 to 255 ? ? ? repeated for lines 2 to 255 sti0-7 application circuit with 6802 processor fig. 10 shows an example of a complete circuit which may be used to evaluate the chip. for convenience, a 4 mhz crystal oscillator has been used rather than a 4.096 mhz clock, as both are within the limits of the chips speci?cations. the rc delay used with the 393 counters ensures a suf?cient hold time for the fp signal, but the values used may have to be changed if faster 393 counters become available. the chip is shown as memory mapped into the mek6802d3 system. chip addresses 00-3f correspond to processor addresses 2000-203f. delay through the address decoder requires the vma signal to be used twice to remove glitches. the mek6802d3 board uses a 10k w pullup on the mr pin, which would have to be incorporated into the circuit if the board was replaced by a processor. figure 9 - four 8980s arranged in a non-blocking 16 x 16 con?guration in 0/7 in 8/15 8980 #1 sti0/7 sto0/7 8980 #2 sti0/7 sto0/7 8980 #3 sti0/7 sto0/7 8980 #4 sti0/7 sto0/7 out 0/7 out 8/15
mt8980d 2-11 figure 10 - application circuit with 6802 mek6802d3 system d7-d0 a15-a0 r/ w mr vma e a15 a14 a13 0v 0v vma 0v 5v 5v 5v a12 a11 a10 0v 0v 0v 0v 0v a9 a8 a7 0v 0v a6 vma 0v 0v 0v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 5v 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 9 10 12 11 md 74 hct 138 md 74 hct 138 md 74 hct 138 md 74 hct 138 md 74 hct 240 dta cs 0v c4i 0v f0i 0v 0v 5v 0v mr 4 mhz 2m w 1 2 3 4 5 6 7 14 13 12 11 10 9 8 5v 5v 0v c4i 0v 0v 0v 0v sn 74 hct 393 sn 74 hct 393 909 w , 1/4w mt 8980 dta sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 vdd f0i c4i a0 a1 a2 a3 a4 a5 ds r/ w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 csto ode sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 vss d0 d1 d2 d3 d4 d5 d6 d7 cs 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 5v 0v 5v 5v 510 w 100pf 5v 1 2 3 4 5 6 7 14 13 12 11 10 9 8
mt8980d 2-12 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. . ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 11 - output test load absolute maximum ratings* parameter symbol min max units 1v dd - v ss -0.3 7 v 2 voltage on digital inputs v i v ss -0.3 v dd +0.3 v 3 voltage on digital outputs v o v ss -0.3 v dd +0.3 v 4 current at digital outputs i o 40 ma 5 storage temperature t s -65 +150 c 6 package power dissipation p d 2w recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 operating temperature t op -40 +85 c 2 positive supply v dd 4.75 5.25 v 3 input voltage v i 0v dd v dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? 1 i n p u t s supply current i dd 6 10 ma outputs unloaded 2 input high voltage v ih 2.0 v 3 input low voltage v il 0.8 v 4 input leakage i il 5 m av i between v ss and v dd 5 input pin capacitance c i 8pf 6 o u t p u t s output high voltage v oh 2.4 v i oh = 10 ma 7 output high current i oh 10 15 ma sourcing. v oh =2.4v 8 output low voltage v ol 0.4 v i ol = 5 ma 9 output low current i ol 5 10 ma sinking. v ol = 0.4v 10 high impedance leakage i oz 5 m av o between v ss and v dd 11 output pin capacitance c o 8pf output pin test point c l v ss s1 r l v dd s2 v ss s1 is open circuit except when testing output levels or high impedance states. s2 is switched to v dd or v ss when testing output levels or high impedance states.
mt8980d 2-13 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * contents of connection memory are not lost if the clock stops, however, st-bus outputs go into the high impedance state. nb: frame pulse is repeated every 512 cycles of c4i. figure 12 - frame alignment figure 13 - clock timing ac electrical characteristics ? - clock timing (figures 12 and 13) characteristics sym min typ ? max units test conditions 1 i n p u t s clock period* t clk 220 244 300 ns 2 clock width high t ch 95 122 150 ns 3 clock width low t cl 110 122 150 ns 4 clock transition time t ctt 20 ns 5 frame pulse setuptime t fps 20 200 ns 6 frame pulse hold time t fph 0.020 50 m s 7 frame pulse width t fpw 244 ns c4i f0i bit cells channel 31 bit o channel 0 bit 7 t clk t ctt t ch t chl t ctt t fph t fps t fph t fps t fpw t cl c4i f0i 2.0v 0.8v 2.0v 0.8v
mt8980d 2-14 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics ? - serial streams (figures 11, 14, 15 and 16) characteristics sym min typ ? max units test conditions 1 o u t p u t s sto0/7 delay - active to high z t saz 20 50 80 ns r l =1 k w * , c l =150 pf 2 sto0/7 delay - high z to active t sza 25 60 125 ns c l =150 pf 3 sto0/7 delay - active to active t saa 30 65 125 ns c l =150 pf 4 sto0/7 hold time t soh 25 45 ns c l =150 pf 5 output driver enable delay t oed 45 125 ns r l =1 k w * , c l =150 pf 6 external control hold time t xch 050 nsc l =150 pf 7 external control delay t xcd 75 110 ns c l =150 pf 8 i n serial input setup time t sis -40 -20 ns 9 serial input hold time t sih 90 ns figure 14 - serial outputs and external control figure 15 - output driver enable figure 16 - serial inputs c4i 2.0v 0.8v sto0 to sto7 2.4v 0.4v sto0 to sto7 2.4v 0.4v sto0 to 2.4v 0.4v csto 2.4v 0.4v bit cell boundary sto7 t soh t saz t sza t soh t saa t xch t xcd * * ode 2.0v 0.8v sto0 to sto7 2.4v 0.4v * t oed t oed * bit cell boundaries c4i 2.0v 0.8v sti0 to sti7 2.0v 0.8v t sis t sih
mt8980d 2-15 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . processor accesses are dependent on the c4i clock, and so some timings are expressed as multiples of the c4i clock period. figure 17 - processor bus ac electrical characteristics ? - processor bus (figures 11 and 17) characteristics sym min typ ? max units test conditions 1 chip select setup time t css 20 0 ns 2 read/write setup time t rws 25 5 ns 3 address setup time t ads 25 5 ns 4 acknowledgement delay fast slow t akd 40 100 ns c l =150 pf t akd 2.7 7.2 cycles c4i cycles 5 fast write data setup time t fws 20 ns 6 slow write data delay t swd 2.0 1.7 cycles c4i cycles 7 read data setup time t rds 0.5 cycles c4i cycles , c l = 150 pf 8 data hold time read write t dht 20 ns r l =1 k w * , c l =150 pf t dht 20 10 ns 9 read data to high impedance t rdz 50 90 ns r l =1 k w * , c l =150 pf 10 chip select hold time t csh 0ns 11 read/write hold time t rwh 0ns 12 address hold time t adh 0ns 13 acknowledgement hold time t akh 10 60 80 ns r l =1 k w * , c l =150 pf ds 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.4v 0.4v 2.4v (read) 2.0v (write) 0.8v (read 0.8v (write) cs r/ w a5 to a0 dta d7 to d0 t css t rws t ads t akd t rds t swd t fws t csh t rwh t adh t akh t dht * * * * t rdz
mt8980d 2-16 notes:
package outlines plastic j-lead chip carrier - p-suf?x f d 1 d h e 1 i a 1 a g d 2 e e 2 dim 20-pin 28-pin 44-pin 68-pin 84-pin min max min max min max min max min max a 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) a 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) d/e 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) d 1 /e 1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) d 2 /e 2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 f 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) g 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) h 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) i 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) for d & e add for allowable mold protrusion 0.010" e: (lead coplanarity) general-10
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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